Difference: FJPPLDetectorRD (22 vs. 23)

Summary:
In recent high energy physics experiments, the data size and trigger rate have much been increased and the software processing on the CPU can cause a bottleneck. In this project, we are going to develop a very fast detector readout system, which can be used for the Belle II experiment. The system receives the data from the detector frontend through optical fibers, performs the event formatting and reduction, and transfer the output to the backend. The board is to be equipped with an up-to-date FPGA (field programmable gate array) chip and the software processing is replaced with an FPGA logic programmed in the hardware language. A high-density optical receivers are implemented on the board to receive a large number of detector signals in order to reduce the total number of readout boards. The outputs are transferred to the backend PC farm through either 10GbE Ethernet or PCI-express interface.
The development requires a high-skill in hardware and firmware development. French group have a lot of experience in developing various FPGA based readout systems. Japanese group are the core members of Belle II DAQ group, who have the accumulated experiences in the readout operation in the Belle and Belle II experiments.

French members:
D. Charlet, C. Beigbeder, E. Kou, F. Le Diberder

Japanese members:
S. Yamada, R. Itoh, M. Nakao

References:
[1] S. Yamada, R. Itoh, K. Nakamura, M. Nakao, S. Y. Suzuki, T. Konno, T. Higuchi, "Data Acquisition System for the Belle II Experiment", IEEE Transactions on Nuclear Science, vol. 62, issue 3, pp. 1175-1180, 2015.
[2] J.P. Cachemiche, P.Y. Duval, F. Hachon, R. Le Gac and F. Rethore, "ThePCIe-based readout system for the LHCb experiment", Topical Workshop on Electronics for Particle Physics, Sep 2015, Lis- bon, Portugal, Journal of Instrumentation 11 (2016) P02013.