Difference: FJPPLNeutrinoPhysics (11 vs. 12)

IN2P3 and University of Tokyo have established a strong collaboration and are co-responsible for both these tasks. To achieve them, an R&D campaign is started with the goal of building a high-speed serial link with embedded clock based on the Field Programmable Gate Arrays (FPGA) serializer-deserializer. The final architecture foreseen a signal that originates from an atomic clock to guarantee a very stable and precise cadence (in the order of 1 ps) associated to a Global Navigation Satellite System (GNSS) receiver to get an UTC reference. It is then distributed, embedded into a data stream, from a master entity to all the front-end nodes. Each front-end extracts the clock with a deterministic phase shift and a less then 100 ps RMS jitter. The data stream is used to exchange critical slow control information between the front-ends and the data acquisition system.