Summary:
The previous project D_RD_02 allowed a ‘proof of principle’ of MPGDs (Micromegas and GEMs) for the electron amplification and readout of a TPC for the Linear Collider. The resolution of such an apparatus was understood and shown to be adequate, and the operation in a beam was demonstrated. Since 2013, a new project was started, as a preparatory step toward the construction of a TPC for the ILD experiment. Integration aspects are now being intensively worked on, including cooling, distortion mitigation and correction, electronics design, gating and other issues, as well as the definition of criteria for the technology choice.

French members:
S. Ganjour, D. Attié, P. Colas, A. Giganon, I. Giomataris, V. Sharyy, B. Tuchming

Japanese members:
K. Fujii, Y. Aoki, T. Fusayasu, K. Kato, M. Kobayashi, T. Matsuda, S. Narita, K. Negishi, T. Ogawa, A. Shoji, A. Sugiyama, T. Takahashi, T. Watanabe

References:
[1] LCTPC Collaboration (David Attié, et al.), "A Time Projection Chamber with GEM-Based Readout", Nucl.Instrum.Meth. A856 (2017) 109-118 [2] W. Wang, ‘A Large Micromegas TPC for the ILC’, Thesis, Université Paris Sud (June 2013)
[3] R. Yonamine, K. Fujii, K. Ikematsu, A. Ishikawa, T. Fusayasu, P. Gros, Y. Kato and S. Kawada et al., “Spatial resolutions of GEM TPC.A novel theoretical formula and its comparison to latest beam test data”, JINST 9, C03002 (2014)
[4] P. Gros, K. Fujii, T. Fusayasu, Y. Kato, S. Kawada, M. Kobayashi, T. Matsuda and O. Nitoh et al., “Blocking positive ion backflow using a GEM gate: experiment and simulations,” JINST 8, C11023 (2013)

Websites:
http://irfu.cea.fr/ILC-TPC/
http://www-jlc.kek.jp/jlc/en/subg/tpc
http://www-hep.phys.saga-u.ac.jp/ILC-TPC/

Summary:
Our aim within the FJPPL is to develop and improve, around French and Japanese collaborators at LAL Orsay, KEK and Tsukuba University, respectively, a strong expertise on tracking detectors for future experiments, with international visibility. The detector upgrade programs underway in ATLAS for HL-LHC will be occasions to improve and optimize the planar pixel technology, which is a particularly well established technology for vertex detectors. The challenge consists in building more granular and thinner P doped sensor devices while keeping the goal of achieving cost effective solutions for large surfaces of sensitive material. This technology, even if it is mature, still needs to prove sufficient radiation hardness in the innermost region, close to the HL-LHC beam crossing environment. The activity within the project includes several of the critical tasks needed to develop this technology.

French members:
A. Lounis, P. Petroff, R. Tanaka, D. Varouchas

Japanese members:
K. Hara, Y. Ikegami, K. Nakamura, H. Okawa, Y. Unno

References:
[1] Achievements of the ATLAS upgrade Planar Pixel Sensors R&D Project, Journal of Instrumentation, JINST 10 C01027, 21 Jan. 2015
[2] Development of novel n+-in-p silicon planar pixel sensors for HL-LHC, Nuclear Instruments and Methods A699 (2013) 72-77
[3] Evaluation of novel KEK/HPK n-in-p pixel sensors for ATLAS upgrade with testbeam, Nuclear Instruments and Methods A699 (2013) 78-83
[4] Leading edge of the technological developments of Planar Pixel Sensors and prospects for ATLAS HL-LHC, A. Lounis, IEEE seoul 2013, proceedings, 22 Nov. 2013

Websites:
http://hep-www.px.tsukuba.ac.jp/~hara/PbulkPixel.html

Summary:
The next generation of lepton colliders (such as the ILC) requires a vertex detector with utmost precision, calling for tiny pixels located very close to the interaction point. The consecutive hit rate generated by the beam related background imposes the pixel read-out to be fast enough to keep the occupancy at an acceptable level. The consecutive complexity of the read-out circuitry, however, relies on a footprint which tends to conflict with the restricted pixel dimensions and can generate sizeable power consumption. The conflict is enhanced by material budget restrictions, which clearly favour monolithic devices instead of hybrid ones;
These observations have motivated a long-term development of various pixel technologies, among which several ones exploiting industrial CMOS processes. The latter have shown to be the most promising among all alternatives considered up to now. The most advanced R&D however did not yet fully solve the conflict between precision, read-out speed and power consumption. It is the objective of the present partnership to overcome the remaining obstacles, its ultimate goal being a single bunch crossing tagging capability with pixels providing a precision better than 3 μm.To reach these target values, the strategy will consist in combining the advantages of the CMOS and SOI technologies in a partnership between two teams concentrating the necessary know-how in both technologies.
The IPHC group has a long history in developing monolithic CMOS Pixel Sensors (CPS). MIMOSA chips are used in a variety of devices, the PXL detector of the STAR experiment (Fig. 1) at BNL acting as a flagship for the benefits of CPS in charmed meson tagging, based on its recently completed 3 years long physics programme.
The Japanese group has been developing monolithic pixel sensors by using a Silicon-on-Insulator (SOI) technology. The SOI detector has both sensor and (CMOS) circuit layers in a wafer as shown in Fig. 2. The process is very flexible, providing great capabilities of developing new detectors. In addition to charged particle detection, both groups are also working for X-Ray detection.
Their partnership will reinforce the development of both technologies due to the enhanced chip designing and testing capabilities. Furthermore, both groups have established relationships with Chinese researcher groups, providing the opportunity of additional synergies.

French members:
M. Winter, J. Baudot, A. Besson, A. Dorokhov, C. Hu-Guo, F. Morel, A. Perez

Japanese members:
Y. Arai, K. Hara, S. Kishimoto, I. Kurachi, T. Miyoshi, M. Togawa, T. Tsuboyama

References:

Websites:
http://rd.kek.jp/project/soi/index.html

Summary:
In recent high energy physics experiments, the data size and trigger rate have much been increased and the software processing on the CPU can cause a bottleneck. In this project, we are going to develop a very fast detector readout system, which can be used for the Belle II experiment. The system receives the data from the detector frontend through optical fibers, performs the event formatting and reduction, and transfer the output to the backend. The board is to be equipped with an up-to-date FPGA (field programmable gate array) chip and the software processing is replaced with an FPGA logic programmed in the hardware language. A high-density optical receivers are implemented on the board to receive a large number of detector signals in order to reduce the total number of readout boards. The outputs are transferred to the backend PC farm through either 10GbE Ethernet or PCI-express interface.
The development requires a high-skill in hardware and firmware development. French group have a lot of experience in developing various FPGA based readout systems. Japanese group are the core members of Belle II DAQ group, who have the accumulated experiences in the readout operation in the Belle and Belle II experiments.

French members:
D. Charlet, C. Beigbeder, E. Kou, F. Le Diberder

Japanese members:
S. Yamada, R. Itoh, M. Nakao

References:
[1] S. Yamada, R. Itoh, K. Nakamura, M. Nakao, S. Y. Suzuki, T. Konno, T. Higuchi, "Data Acquisition System for the Belle II Experiment", IEEE Transactions on Nuclear Science, vol. 62, issue 3, pp. 1175-1180, 2015.
[2] J.P. Cachemiche, P.Y. Duval, F. Hachon, R. Le Gac and F. Rethore, "ThePCIe-based readout system for the LHCb experiment", Topical Workshop on Electronics for Particle Physics, Sep 2015, Lis- bon, Portugal, Journal of Instrumentation 11 (2016) P02013.